Programmable logic devices such as field programmable gate arrays (FPGAs) include a number of logic blocks that are interconnected by a programmable interconnect, also referred to as a routing structure. The programmable routing structure provides the routing for bringing input signals to the logic blocks as well as transmitting output signals from the logic blocks. Thus, the programmable routing structure may be configured to provide input signals to any given logic block either from input/output (I/O) circuits or from other logic blocks. Similarly, the programmable routing structure may be configured to route output signals from any given logic block to other logic blocks or to the I/O circuits.
A conventional field programmable gate array (FPGA) 100 is illustrated in FIG. 1. As is conventional in the programmable logic arts, logic blocks 120 in FPGA 100 are organized in a row and column fashion. In this exemplary embodiment, there are three rows R1 through R3 of programmable logic blocks 120. Similarly, there are three columns C1 through C3 of logic blocks 120. The routing structure for FPGA 100 is also organized in a row and column fashion. Thus, each row R1 through R3 includes a corresponding horizontal routing resource 130 whereas each column C1 through C3 includes a corresponding vertical routing resource 140.
Typically, each of these routing resources (which may include multiple switches, buffers, and wires) is segmented. For example, FIG. 2 illustrates a portion 200 of a routing resource with respect to a logic block 120. As illustrated, portion 200 routes in the horizontal direction but it will be appreciated that such an orientation is arbitrary in that portion 200 could also be taken from a vertical routing resource. A first routing segment X1 allows signals to flow between logic block 120 and an immediately adjacent logic block (not illustrated). With respect to FIG. 2, the immediately adjacent logic block would be located in the same row of logic blocks that contains logic block 120. Similarly, if portion 200 were taken from a vertical routing resource, the immediately adjacent logic block would be located in the same column of logic blocks that contains logic block 120. A second routing segment X2 allows signals to flow between logic block 120 and a logic block in the same row two blocks away, thereby spanning three blocks. Similarly, a third routing segment X3 allows signals to flow between logic block 120 and a logic block in the same row three blocks away. In general, a routing segment “XN” would denote a segment that spans an integer N+1 of logic blocks.
Regardless of the number or type of segments in the routing structure, a connection to external devices or signals is generally needed. For example, referring back to FIG. 1, FPGA 100 includes I/O circuits 150 that communicate with pins 160. As known in the art, signals can either flow into or out of FPGA 100 through pins 160. A number of different signaling protocols may be used for these signals such as LVCMOS 3.3V, LVCMOS 2.5V, LVCMOS 1.8V, LVDS, and others. I/O circuits 150 function to translate the external signaling protocol and the internal signaling protocol used within FPGA 100.
An FPGA 100 will typically include configurable interface blocks (CIBs) 170 through which horizontal and vertical routing resources 130 and 140 are coupled to I/O circuits 150. Connection boxes (also referred to as switch boxes or connection blocks) couple signals to and from logic blocks 120 to these routing resources. Turning now to FIG. 3a, the relationship between a logic block 120 and a corresponding connection box 300 (which may also be denoted as a switch box 300) is illustrated. Switch box 300 includes input and output switch matrices to flexibly route signals between horizontal and vertical routing resources 130 and 140 and logic block 120. In the embodiment illustrated, horizontal and vertical routing resources are segmented routing resources including segments X1, X2, and X8. Regardless of whether the routing resources are segmented, input signals may route through switch box 300 from the routing resources as lookup table inputs for lookup tables (LUTs) (discussed with respect to FIG. 3b) within logic block 120. Similarly, output signals from these LUTs may route through switch box 300 into routing resources 130 and 140.
A “bank” approach to organizing routing resources 130 and 140 with respect to this routing through switch box 300 is conventional. With respect to a segmented routing architecture, each bank represents a group of horizontal wires and associated group of vertical wire of the same segment length. For example, as seen in FIG. 3b, the X2 horizontal wires may be organized into two groups denoted as horizontal bundle 0 and horizontal bundle 1. Similarly, the X2 vertical wires may be organized into two groups denoted as vertical bundle 0 and vertical bundle 1. Horizontal bundle 0 and vertical bundle 0 form bank 0, and Horizontal bundle 1 and vertical bundle 1 form bank 1. A LUT 0 and a LUT 1 within logic block 120 (FIG. 3a) are shown. For illustration clarity, each bundle comprises just two wires each and each LUT receives just two input signals. LUT 0 receives input signals at inputs A0 and B0 whereas LUT 1 receives input signals at inputs A1 and B1. With respect to selection of these input signals from the simplified X2 routing shown in FIG. 3b, an input switch matrix 310 within switch box 300 (FIG. 3a) may comprise 4:1 multiplexers 320. It will be appreciated by those of ordinary skill in the art that input switch matrix 310 includes a plurality of “fuse points” controlled by configuration memory cells so that wires in the routing structure may be coupled to LUT inputs. For illustration clarity, these fuse points are not shown and are represented by multiplexers 320. A first 4:1 multiplexer 320a selects a signal from the wires in bank 0 (horizontal bundle 0 and vertical bundle 0) for input A0. A second 4:1 multiplexer 320b selects a signal from the wires in bank 1 (horizontal bundle 1 and vertical bundle 1) for input B0. Similarly, a third multiplexer 320c selects a signal from bank 0 to for input A1 whereas a fourth multiplexer 320d selects a signal from bank 1 for input B1.
Because the routing is bank-based, signals on one wire bundle within a bank cannot be routed independently of signals on another wire bundle within the same bank. For example, because horizontal bundle 0 and vertical bundle 0 form bank 0, input switch matrix 310 in each of LUT 0 and LUT 1 is configurable to route only a signal from horizontal bundle 0 or vertical bundle 0 to a one LUT input (A0 or A1) and to route only a signal from horizontal bundle 1 or vertical bundle 1 to the other LUT input (B0 or B1).
Although a bank-based routing architecture has proven to be very popular for routing because of its flexibility, the semiconductor die area for the necessary input switch boxes can be considerable. In addition, a significant portion of the total routing delay and power consumption occurs in the switch boxes. Accordingly, there is a need in the art for an improved routing architecture that provides sufficient routing flexibility yet alleviates these problems.